PWM_SCM

PWM Sync Channels Mode Register

This register can only be written if bits WPSWS2 and WPHWS2 are cleared in the PWM Write Protection Status Register.

  0x20 32 Read/Write 0x00000000  
Parent topic: Register Summary

PWM Sync Channels Mode Register

Bit  31 30 29 28 27 26 25 24  
                   
Access                   
Reset                   
Bit  23 22 21 20 19 18 17 16  
  PTRCS[2:0] PTRM     UPDM[1:0]  
Access  R/W R/W R/W R/W     R/W R/W  
Reset  0 0 0 0     0 0  
Bit  15 14 13 12 11 10 9 8  
                   
Access                   
Reset                   
Bit  7 6 5 4 3 2 1 0  
          SYNC3 SYNC2 SYNC1 SYNC0  
Access          R/W R/W R/W R/W  
Reset          0 0 0 0  

Bits 0, 1, 2, 3 – SYNCx: Synchronous Channel x

Synchronous Channel x

ValueDescription
0

Channel x is not a synchronous channel.
1

Channel x is a synchronous channel.

Bits 17:16 – UPDM[1:0]: Synchronous Channels Update Mode

Synchronous Channels Update Mode

Notes:
  1. 1.The update occurs at the beginning of the next PWM period, when the UPDULOCK bit in PWM Sync Channels Update Control Register is set.
  2. 2.The update occurs when the Update Period is elapsed.
ValueNameDescription
0 MODE0

Manual write of double buffer registers and manual update of synchronous channels 1(1).
1 MODE1

Manual write of double buffer registers and automatic update of synchronous channels 2(2).
2 MODE2

The WRDY flag in PWM Interrupt Status Register 2 and the DMA transfer request are set to ‘1’ as soon as the update period is elapsed.

Bit 20 – PTRM: DMA Controller Transfer Request Mode

DMA Controller Transfer Request Mode

UPDM

PTRM

 WRDY Flag and DMA Controller Transfer Request
0 x The WRDY flag in PWM Interrupt Status Register 2 and the DMA transfer request are never set to ‘1’.
1 x The WRDY flag in PWM Interrupt Status Register 2 is set to ‘1’ as soon as the update period is elapsed, the DMA Controller transfer request is never set to ‘1’.
2 0 The WRDY flag in PWM Interrupt Status Register 2 and the DMA transfer request are set to ‘1’ as soon as the update period is elapsed.
1 The WRDY flag in PWM Interrupt Status Register 2 and the DMA transfer request are set to ‘1’ as soon as the selected comparison matches.

Bits 23:21 – PTRCS[2:0]: DMA Controller Transfer Request Comparison Selection

DMA Controller Transfer Request Comparison Selection

Selection of the comparison used to set the flag WRDY and the corresponding DMA Controller transfer request.