SPI_CSRx

SPI Chip Select Register

This register can only be written if the WPEN bit is cleared in the SPI Write Protection Mode Register.

SPI_CSRx must be written even if the user wants to use the default reset values. The BITS field is not updated with the translated value unless the register is written.

0x30 + x*0x04 [x=0..3] 32 R/W 0 4 -1

SPI Chip Select Register
CPOL
Clock Polarity
NCPHA
Clock Phase
CSNAAT
Chip Select Not Active After Transfer (ignored if CSAAT = 1)
CSAAT
Chip Select Active After Transfer
BITS
Bits Per Transfer
SCBR
Serial Clock Bit Rate
DLYBS
Delay Before SPCK
DLYBCT
Delay Between Consecutive Transfers

SPI Chip Select Register

Bit	31	30	29	28	27	26	25	24
	DLYBCT[7:0]
Access	R/W	R/W	R/W	R/W	R/W	R/W	R/W	R/W
Reset	0	0	0	0	0	0	0	0

Bit	23	22	21	20	19	18	17	16
	DLYBS[7:0]
Access	R/W	R/W	R/W	R/W	R/W	R/W	R/W	R/W
Reset	0	0	0	0	0	0	0	0

Bit	15	14	13	12	11	10	9	8
	SCBR[7:0]
Access	R/W	R/W	R/W	R/W	R/W	R/W	R/W	R/W
Reset	0	0	0	0	0	0	0	0

Bit	7	6	5	4	3	2	1	0
	BITS[3:0]				CSAAT	CSNAAT	NCPHA	CPOL
Access	R/W	R/W	R/W	R/W	R/W	R/W	R/W	R/W
Reset	0	0	0	0	0	0	0	0

Bit 0 – CPOL: Clock Polarity

Clock Polarity

CPOL is used to determine the inactive state value of the serial clock (SPCK). It is used with NCPHA to produce the required clock/data relationship between master and slave devices.

Value	Description
0	The inactive state value of SPCK is logic level zero.
1	The inactive state value of SPCK is logic level one.

Bit 1 – NCPHA: Clock Phase

Clock Phase

NCPHA determines which edge of SPCK causes data to change and which edge causes data to be captured. NCPHA is used with CPOL to produce the required clock/data relationship between master and slave devices.

Value	Description
0	Data is changed on the leading edge of SPCK and captured on the following edge of SPCK.
1	Data is captured on the leading edge of SPCK and changed on the following edge of SPCK.

Bit 2 – CSNAAT: Chip Select Not Active After Transfer (ignored if CSAAT = 1)

Chip Select Not Active After Transfer (ignored if CSAAT = 1)

Value	Description
0	The Peripheral Chip Select Line does not rise between two transfers if SPI_TDR is reloaded before the end of the first transfer and if the two transfers occur on the same chip select.
1	The Peripheral Chip Select Line rises systematically after each transfer performed on the same slave. It remains inactive after the end of transfer for a minimal duration of: DLYBCSfperipheral clock (If field DLYBCS is lower than 6, a minimum of six periods is introduced.)

Value

Description

The Peripheral Chip Select Line does not rise between two transfers if SPI_TDR is reloaded before the end of the first transfer and if the two transfers occur on the same chip select.

The Peripheral Chip Select Line rises systematically after each transfer performed on the same slave. It remains inactive after the end of transfer for a minimal duration of:

DLYBCSfperipheral clock (If field DLYBCS is lower than 6, a minimum of six periods is introduced.)

Bit 3 – CSAAT: Chip Select Active After Transfer

Chip Select Active After Transfer

Value	Description
0	The Peripheral Chip Select Line rises as soon as the last transfer is achieved.
1	The Peripheral Chip Select Line does not rise after the last transfer is achieved. It remains active until a new transfer is requested on a different chip select.

Bits 7:4 – BITS[3:0]: Bits Per Transfer

Bits Per Transfer

(See Note under the register table in SPI Chip Select Register.)

The BITS field determines the number of data bits transferred. Reserved values should not be used.

Value	Name	Description
0	8_BIT	8 bits for transfer
1	9_BIT	9 bits for transfer
2	10_BIT	10 bits for transfer
3	11_BIT	11 bits for transfer
4	12_BIT	12 bits for transfer
5	13_BIT	13 bits for transfer
6	14_BIT	14 bits for transfer
7	15_BIT	15 bits for transfer
8	16_BIT	16 bits for transfer
9	–	Reserved
10	–	Reserved
11	–	Reserved
12	–	Reserved
13	–	Reserved
14	–	Reserved
15	–	Reserved

Bits 15:8 – SCBR[7:0]: Serial Clock Bit Rate

Serial Clock Bit Rate

In Master mode, the SPI Interface uses a modulus counter to derive the SPCK bit rate from the peripheral clock. The bit rate is selected by writing a value from1 to 255 in the SCBR field. The following equation determines the SPCK bit rate:

SCBR = f_{peripheral
clock} / SPCK Bit Rate

Programming the SCBR field to 0 is forbidden. Triggering a transfer while SCBR is at 0 can lead to unpredictable results.

At reset, SCBR is 0 and the user has to program it at a valid value before performing the first transfer.

Note: If one of the SCBR fields in SPI_CSRx is set to 1, the other SCBR fields in SPI_CSRx must be set to 1 as well, if they are used to process transfers. If they are not used to transfer data, they can be set at any value.

Bits 23:16 – DLYBS[7:0]: Delay Before SPCK

Delay Before SPCK

This field defines the delay from NPCS falling edge (activation) to the first valid SPCK transition.

When DLYBS = 0, the delay is half the SPCK clock period.

Otherwise, the following equation determines the delay:

DLYBS = Delay Before SPCK × f_{peripheral clock}

Bits 31:24 – DLYBCT[7:0]: Delay Between Consecutive Transfers

Delay Between Consecutive Transfers

This field defines the delay between two consecutive transfers with the same peripheral without removing the chip select. The delay is always inserted after each transfer and before removing the chip select if needed.

When DLYBCT = 0, no delay between consecutive transfers is inserted and the clock keeps its duty cycle over the character transfers.

Otherwise, the following equation determines the delay:

DLYBCT = Delay Between Consecutive Transfers × f_{peripheral clock} / 32