User Signature Area

Each product contains a user signature area of 512 bytes. It can be used for storage. Read, write, and erase of this area is allowed. Refer to “Flash Memory Areas”.

The sequence to read the user signature area is as follows:

  1. 1.Execute the ‘Start Read User Signature’ command by writing EEFC_FCR.FCMD with the STUS command. Field EEFC_FCR.FARG is meaningless.
  2. 2.Wait until the EEFC_FSR.FRDY bit falls to read the user signature area. The user signature area is located in the first 512 bytes of the Flash memory mapping. The ‘Start Read User Signature’ command reuses some addresses of the memory plane but the user signature area is physically different from the memory plane
  3. 3.To stop reading the user signature area, execute the ‘Stop Read User Signature’ command by writing EEFC_FCR.FCMD with the SPUS command. Field EEFC_FCR.FARG is meaningless.
  4. 4.When the SPUI command has been executed, the bit EEFC_FSR.FRDY rises. If an interrupt was enabled by setting the bit EEFC_FMR.FRDY, the interrupt line of the interrupt controller is activated.
Note: During the sequence, the software cannot be fetched from the Flash or from the second plane in case of dual plane.

One error can be detected in EEFC_FSR after this sequence:

The sequence to write the user signature area is as follows:

  1. 1.Write the full page, at any page address, within the internal memory area address space.
  2. 2.Execute the ‘Write User Signature’ command by writing EEFC_FCR.FCMD with the WUS command. Field EEFC_FCR.FARG is meaningless.
  3. 3.When programming is completed, the EEFC_FSR.FRDY bit rises. If an interrupt has been enabled by setting the EEFC_FMR.FRDY bit, the corresponding interrupt line of the interrupt controller is activated.

The following two errors can be detected in EEFC_FSR after this sequence:

The sequence to erase the user signature area is as follows:

  1. 1.Execute the ‘Erase User Signature’ command by writing EEFC_FCR.FCMD with the EUS command. Field EEFC_FCR.FARG is meaningless.
  2. 2.When programming is completed, the EEFC_FSR.FRDY bit rises. If an interrupt has been enabled by setting the EEFC_FMR.FRDY bit, the corresponding interrupt line of the interrupt controller is activated.

Two errors can be detected in EEFC_FSR after this sequence: