QSPI Interrupt Disable Register
The following configuration values are valid for all listed bit names of this register:
0: No effect.
1: Disables the corresponding interrupt.
Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
Access | |||||||||
Reset |
Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
Access | |||||||||
Reset |
Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
INSTRE | CSS | CSR | |||||||
Access | W | W | W | ||||||
Reset | – | – | – |
Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
OVRES | TXEMPTY | TDRE | RDRF | ||||||
Access | W | W | W | W | |||||
Reset | – | – | – | – |
Receive Data Register Full Interrupt Disable
Transmit Data Register Empty Interrupt Disable
Transmission Registers Empty Disable
Overrun Error Interrupt Disable
Chip Select Rise Interrupt Disable
Chip Select Status Interrupt Disable
Instruction End Interrupt Disable