QSPI_IDR

QSPI Interrupt Disable Register

The following configuration values are valid for all listed bit names of this register:

0: No effect.

1: Disables the corresponding interrupt.

  0x18 32 Write-only –  

QSPI Interrupt Disable Register

Bit  31 30 29 28 27 26 25 24  
                   
Access                   
Reset                   
Bit  23 22 21 20 19 18 17 16  
                   
Access                   
Reset                   
Bit  15 14 13 12 11 10 9 8  
            INSTRE CSS CSR  
Access            W W W  
Reset             
Bit  7 6 5 4 3 2 1 0  
          OVRES TXEMPTY TDRE RDRF  
Access          W W W W  
Reset           

Bit 0 – RDRF: Receive Data Register Full Interrupt Disable

Receive Data Register Full Interrupt Disable

Bit 1 – TDRE: Transmit Data Register Empty Interrupt Disable

Transmit Data Register Empty Interrupt Disable

Bit 2 – TXEMPTY: Transmission Registers Empty Disable

Transmission Registers Empty Disable

Bit 3 – OVRES: Overrun Error Interrupt Disable

Overrun Error Interrupt Disable

Bit 8 – CSR: Chip Select Rise Interrupt Disable

Chip Select Rise Interrupt Disable

Bit 9 – CSS: Chip Select Status Interrupt Disable

Chip Select Status Interrupt Disable

Bit 10 – INSTRE: Instruction End Interrupt Disable

Instruction End Interrupt Disable