PWM_CDTYUPDx

PWM Channel Duty Cycle Update Register

This register acts as a double buffer for the CDTY value. This prevents an unexpected waveform when modifying the waveform duty-cycle.

Only the first 16 bits (channel counter size) are significant.

  0x0208 + x*0x20 [x=0..3] 32 Write-only –   4 32 -1
Parent topic: Register Summary

PWM Channel Duty Cycle Update Register

Bit  31 30 29 28 27 26 25 24  
                   
Access                   
Reset                   
Bit  23 22 21 20 19 18 17 16  
  CDTYUPD[23:16]  
Access  W W W W W W W W  
Reset  0 0 0 0 0 0 0 0  
Bit  15 14 13 12 11 10 9 8  
  CDTYUPD[15:8]  
Access  W W W W W W W W  
Reset  0 0 0 0 0 0 0 0  
Bit  7 6 5 4 3 2 1 0  
  CDTYUPD[7:0]  
Access  W W W W W W W W  
Reset  0 0 0 0 0 0 0 –  

Bits 23:0 – CDTYUPD[23:0]: Channel Duty-Cycle Update

Channel Duty-Cycle Update

Defines the waveform duty-cycle. This value must be defined between 0 and CPRD (PWM_CPRDx).