USART Interrupt Enable Register (LIN_MODE)
This configuration is relevant only if USART_MODE = 0xA or 0xB in the USART Mode Register.
The following configuration values are valid for all listed bit names of this register:
0: No effect
1: Enables the corresponding interrupt.
Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
LINHTE | LINSTE | LINSNRE | LINCE | LINIPE | LINISFE | LINBE | |||
Access | |||||||||
Reset |
Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
Access | |||||||||
Reset |
Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
LINTC | LINID | LINBK | TXEMPTY | TIMEOUT | |||||
Access | |||||||||
Reset |
Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
PARE | FRAME | OVRE | TXRDY | RXRDY | |||||
Access | |||||||||
Reset |
RXRDY Interrupt Enable
TXRDY Interrupt Enable
Overrun Error Interrupt Enable
Framing Error Interrupt Enable
Parity Error Interrupt Enable
Timeout Interrupt Enable
TXEMPTY Interrupt Enable
LIN Break Sent or LIN Break Received Interrupt Enable
LIN Identifier Sent or LIN Identifier Received Interrupt Enable
LIN Transfer Completed Interrupt Enable
LIN Bus Error Interrupt Enable
LIN Inconsistent Synch Field Error Interrupt Enable
LIN Identifier Parity Interrupt Enable
LIN Checksum Error Interrupt Enable
LIN Slave Not Responding Error Interrupt Enable
LIN Synch Tolerance Error Interrupt Enable
LIN Header Timeout Error Interrupt Enable