Max speed mode is enabled by setting DACC_TRIGR.TRGENx and DACC_MR.MAXSx.
The conversion rate is forced by the controller, which starts one conversion every 12 DAC clock periods. The controller does not wait for the EOC of the previous data to send a new data to the DAC and the DAC is always clocked.
If the FIFO is emptied, the controller send the last converted data to the DAC at a rate of 12 DAC clock periods.
The DACC_ACR.IBCTLCHx field must be configured for 1 MSps (see the section “Electrical Characteristics”).
Figure 1. Conversion Sequence in Max Speed Mode
