RSWDT_MR

Reinforced Safety Watchdog Timer Mode Register

Note: The first write access prevents any further modification of the value of this register; read accesses remain possible. The WDV value must not be modified within three slow clock periods following a restart of the watchdog performed by means of a write access in the RSWDT_CR, else the watchdog may trigger an end of period earlier than expected.
  0x04 32 Read/Write Once 0x3FFFAFFF  
Parent topic: Register Summary

Reinforced Safety Watchdog Timer Mode Register

Bit  31 30 29 28 27 26 25 24  
      WDIDLEHLT WDDBGHLT ALLONES[11:8]  
Access                   
Reset      1 1 1 1 1 1  
Bit  23 22 21 20 19 18 17 16  
  ALLONES[7:0]  
Access                   
Reset  1 1 1 1 1 1 1 1  
Bit  15 14 13 12 11 10 9 8  
  WDDIS   WDRSTEN WDFIEN WDV[11:8]  
Access                   
Reset  1   1 0 1 1 1 1  
Bit  7 6 5 4 3 2 1 0  
  WDV[7:0]  
Access                   
Reset  1 1 1 1 1 1 1 1  

Bits 11:0 – WDV[11:0]: Watchdog Counter Value

Watchdog Counter Value

Defines the value loaded in the 12-bit watchdog counter.

Bit 12 – WDFIEN: Watchdog Fault Interrupt Enable

Watchdog Fault Interrupt Enable

ValueDescription
0 A Watchdog fault (underflow or error) has no effect on interrupt.
1 A Watchdog fault (underflow or error) asserts interrupt.

Bit 13 – WDRSTEN: Watchdog Reset Enable

Watchdog Reset Enable

ValueDescription
0 A Watchdog fault (underflow or error) has no effect on the resets.
1 A Watchdog fault (underflow or error) triggers a watchdog reset.

Bits 27:16 – ALLONES[11:0]: Must Always Be Written with 0xFFF

Must Always Be Written with 0xFFF

Bit 28 – WDDBGHLT: Watchdog Debug Halt

Watchdog Debug Halt

ValueDescription
0 The RSWDT runs when the processor is in debug state.
1 The RSWDT stops when the processor is in debug state.

Bit 29 – WDIDLEHLT: Watchdog Idle Halt

Watchdog Idle Halt

ValueDescription
0 The RSWDT runs when the system is in idle mode.
1 The RSWDT stops when the system is in idle state.

Bit 15 – WDDIS: Watchdog Disable

Watchdog Disable

ValueDescription
0 Enables the RSWDT.
1 Disables the RSWDT.