Device Endpoint Interrupt Enable Register (Control, Bulk, Interrupt Endpoints)
This register view is relevant only if EPTYPE = 0x0, 0x2, or 0x3 in ”Device Endpoint x Configuration Register”.
For additional information, see ”Device Endpoint x Mask Register (Control, Bulk, Interrupt Endpoints)”.
This register always reads as zero.
The following configuration values are valid for all listed bit names of this register:
0: No effect.
1: Sets the corresponding bit in USBHS_DEVEPTIMRx.
Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
Access | |||||||||
Reset |
Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
STALLRQS | RSTDTS | NYETDISS | EPDISHDMAS | ||||||
Access | |||||||||
Reset | 0 | 0 | 0 | 0 |
Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
FIFOCONS | KILLBKS | NBUSYBKES | |||||||
Access | |||||||||
Reset | 0 | 0 | 0 |
Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
SHORTPACKETES | STALLEDES | OVERFES | NAKINES | NAKOUTES | RXSTPES | RXOUTES | TXINES | ||
Access | |||||||||
Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
Transmitted IN Data Interrupt Enable
Received OUT Data Interrupt Enable
Received SETUP Interrupt Enable
NAKed OUT Interrupt Enable
NAKed IN Interrupt Enable
Overflow Interrupt Enable
STALLed Interrupt Enable
Short Packet Interrupt Enable
Number of Busy Banks Interrupt Enable
Kill IN Bank
FIFO Control
Endpoint Interrupts Disable HDMA Request Enable
NYET Token Disable Enable
Reset Data Toggle Enable
STALL Request Enable