Host Global Interrupt Set Register
This register always reads as zero.
The following configuration values are valid for all listed bit names of this register:
0: No effect.
1: Sets the corresponding bit in USBHS_HSTISR, which may be useful for test or debug purposes.
Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
DMA_6 | DMA_5 | DMA_4 | DMA_3 | DMA_2 | DMA_1 | DMA_0 | |||
Access | |||||||||
Reset |
Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
Access | |||||||||
Reset |
Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
Access | |||||||||
Reset |
Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
HWUPIS | HSOFIS | RXRSMIS | RSMEDIS | RSTIS | DDISCIS | DCONNIS | |||
Access | |||||||||
Reset |
Device Connection Interrupt Set
Device Disconnection Interrupt Set
USB Reset Sent Interrupt Set
Downstream Resume Sent Interrupt Set
Upstream Resume Received Interrupt Set
Host Start of Frame Interrupt Set
Host Wakeup Interrupt Set
DMA Channel x Interrupt Set