SSC_IMR

SSC Interrupt Mask Register

  0x4C 32 Read-only 0x00000000  
Parent topic: Register Summary

SSC Interrupt Mask Register

Bit  31 30 29 28 27 26 25 24  
                   
Access                   
Reset                   
Bit  23 22 21 20 19 18 17 16  
                   
Access                   
Reset                   
Bit  15 14 13 12 11 10 9 8  
          RXSYN TXSYN CP1 CP0  
Access          R R R R  
Reset          0 0 0 0  
Bit  7 6 5 4 3 2 1 0  
      OVRUN RXRDY     TXEMPTY TXRDY  
Access      R R     R R  
Reset      0 0     0 0  

Bit 0 – TXRDY: Transmit Ready Interrupt Mask

Transmit Ready Interrupt Mask

ValueDescription
0

The Transmit Ready Interrupt is disabled.
1

The Transmit Ready Interrupt is enabled.

Bit 1 – TXEMPTY: Transmit Empty Interrupt Mask

Transmit Empty Interrupt Mask

ValueDescription
0

The Transmit Empty Interrupt is disabled.
1

The Transmit Empty Interrupt is enabled.

Bit 4 – RXRDY: Receive Ready Interrupt Mask

Receive Ready Interrupt Mask

ValueDescription
0

The Receive Ready Interrupt is disabled.
1

The Receive Ready Interrupt is enabled.

Bit 5 – OVRUN: Receive Overrun Interrupt Mask

Receive Overrun Interrupt Mask

ValueDescription
0

The Receive Overrun Interrupt is disabled.
1

The Receive Overrun Interrupt is enabled.

Bit 8 – CP0: Compare 0 Interrupt Mask

Compare 0 Interrupt Mask

ValueDescription
0

The Compare 0 Interrupt is disabled.
1

The Compare 0 Interrupt is enabled.

Bit 9 – CP1: Compare 1 Interrupt Mask

Compare 1 Interrupt Mask

ValueDescription
0

The Compare 1 Interrupt is disabled.
1

The Compare 1 Interrupt is enabled.

Bit 10 – TXSYN: Tx Sync Interrupt Mask

Tx Sync Interrupt Mask

ValueDescription
0

The Tx Sync Interrupt is disabled.
1

The Tx Sync Interrupt is enabled.

Bit 11 – RXSYN: Rx Sync Interrupt Mask

Rx Sync Interrupt Mask

ValueDescription
0

The Rx Sync Interrupt is disabled.
1

The Rx Sync Interrupt is enabled.