MCAN Receive FIFO 0 Configuration
This register can only be written if the bits CCE and INIT are set in MCAN CC Control Register.
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| F0OM | F0WM[6:0] | ||||||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| F0S[6:0] | |||||||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | ||
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | ||
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| F0SA[13:6] | |||||||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| F0SA[5:0] | |||||||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | |||
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | |||
Receive FIFO 0 Start Address
Start address of Receive FIFO 0 in Message RAM (32-bit word address, see Message RAM Configuration).
Write F0SA with the bits [15:2] of the 32-bit address.
Receive FIFO 0 Size
The Receive FIFO 0 elements are indexed from 0 to F0S-1.
| Value | Description |
|---|---|
| 0 | No Receive FIFO 0 |
| 1-64 | Number of Receive FIFO 0 elements. |
| >64 |
Values greater than 64 are interpreted as 64. |
Receive FIFO 0 Watermark
| Value | Description |
|---|---|
| 0 | Watermark interrupt disabled. |
| 1-64 | Level for Receive FIFO 0 watermark interrupt (MCAN_IR.RF0W). |
| >64 |
Watermark interrupt disabled. |
FIFO 0 Operation Mode
FIFO 0 can be operated in Blocking or in Overwrite mode (see Rx FIFOs).
| Value | Description |
|---|---|
| 0 | FIFO 0 Blocking mode. |
| 1 | FIFO 0 Overwrite mode. |