Real-time Timer Mode Register
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| RTC1HZ | |||||||||
| Access | |||||||||
| Reset | 0 |
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| RTTDIS | RTTRST | RTTINCIEN | ALMIEN | ||||||
| Access | R/W | R/W | R/W | ||||||
| Reset | 0 | 0 | 0 | 0 |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| RTPRES[15:8] | |||||||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
| Reset | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| RTPRES[7:0] | |||||||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
Real-time Timer Prescaler Value
RTPRES is defined as follows:
Alarm Interrupt Enable
| Value | Description |
|---|---|
| 0 |
The bit ALMS in RTT_SR has no effect on interrupt. |
| 1 |
The bit ALMS in RTT_SR asserts interrupt. |
Real-time Timer Increment Interrupt Enable
| Value | Description |
|---|---|
| 0 |
The bit RTTINC in RTT_SR has no effect on interrupt. |
| 1 |
The bit RTTINC in RTT_SR asserts interrupt. |
Real-time Timer Restart
| Value | Description |
|---|---|
| 0 |
No effect. |
| 1 |
Reloads and restarts the clock divider with the new programmed value. This also resets the 32-bit counter. |
Real-time Timer Disable
| Value | Description |
|---|---|
| 0 |
The RTT is enabled. |
| 1 |
The RTT is disabled (no dynamic power consumption). |
Real-Time Clock 1Hz Clock Selection
| Value | Description |
|---|---|
| 0 | The RTT 32-bit counter is driven by the 16-bit prescaler roll-over events. |
| 1 |
The RTT 32-bit counter is driven by the 1Hz RTC clock. |