QSPI_IFR

QSPI Instruction Frame Register

0x38 32 Read/Write 0x00000000

QSPI Instruction Frame Register
WIDTH
Width of Instruction Code, Address, Option Code and Data
INSTEN
Instruction Enable
ADDREN
Address Enable
OPTEN
Option Enable
DATAEN
Data Enable
OPTL
Option Code Length
ADDRL
Address Length
TFRTYP
Data Transfer Type
CRM
Continuous Read Mode
DDREN
DDR Mode Enable
NBDUM
Number Of Dummy Cycles
APBTFRTYP
APB Transfer Type
DDRCMDEN
DDR Mode Command Enable

QSPI Instruction Frame Register

Bit	31	30	29	28	27	26	25	24
						DDRCMDEN		APBTFRTYP
Access						R/W		R/W
Reset						0		0

Bit	23	22	21	20	19	18	17	16
				NBDUM[4:0]
Access
Reset				0	0	0	0	0

Bit	15	14	13	12	11	10	9	8
	DDREN	CRM		TFRTYP		ADDRL	OPTL[1:0]
Access	R/W	R/W		R/W		R/W	R/W	R/W
Reset	0	0		0		0	0	0

Bit	7	6	5	4	3	2	1	0
	DATAEN	OPTEN	ADDREN	INSTEN		WIDTH[2:0]
Access	R/W	R/W	R/W	R/W		R/W	R/W	R/W
Reset	0	0	0	0		0	0	0

Bits 2:0 – WIDTH[2:0]: Width of Instruction Code, Address, Option Code and Data

Width of Instruction Code, Address, Option Code and Data

Value	Name	Description
0	SINGLE_BIT_SPI	Instruction: Single-bit SPI / Address-Option: Single-bit SPI / Data: Single-bit SPI
1	DUAL_OUTPUT	Instruction: Single-bit SPI / Address-Option: Single-bit SPI / Data: Dual SPI
2	QUAD_OUTPUT	Instruction: Single-bit SPI / Address-Option: Single-bit SPI / Data: Quad SPI
3	DUAL_IO	Instruction: Single-bit SPI / Address-Option: Dual SPI / Data: Dual SPI
4	QUAD_IO	Instruction: Single-bit SPI / Address-Option: Quad SPI / Data: Quad SPI
5	DUAL_CMD	Instruction: Dual SPI / Address-Option: Dual SPI / Data: Dual SPI
6	QUAD_CMD	Instruction: Quad SPI / Address-Option: Quad SPI / Data: Quad SPI

Bit 4 – INSTEN: Instruction Enable

Instruction Enable

Value	Description
0	The instruction is not sent to the serial Flash memory.
1	The instruction is sent to the serial Flash memory.

Bit 5 – ADDREN: Address Enable

Address Enable

Value	Description
0	The transfer address is not sent to the serial Flash memory.
1	The transfer address is sent to the serial Flash memory.

Bit 6 – OPTEN: Option Enable

Option Enable

Value	Description
0	The option is not sent to the serial Flash memory.
1	The option is sent to the serial Flash memory.

Bit 7 – DATAEN: Data Enable

Data Enable

Value	Description
0	No data is sent/received to/from the serial Flash memory.
1	Data is sent/received to/from the serial Flash memory.

Bits 9:8 – OPTL[1:0]: Option Code Length

Option Code Length

The OPTL field determines the length of the option code. The value written in OPTL must be consistent with the value written in the field WIDTH. For example, OPTL = 0 (1-bit option code) is not consistent with WIDTH = 6 (option code sent with QuadSPI protocol, thus the minimum length of the option code is 4 bits).

Value	Name	Description
0	OPTION_1BIT	The option code is 1 bit long.
1	OPTION_2BIT	The option code is 2 bits long.
2	OPTION_4BIT	The option code is 4 bits long.
3	OPTION_8BIT	The option code is 8 bits long.

Bit 10 – ADDRL: Address Length

Address Length

The ADDRL bit determines the length of the address.

0 (24_BIT): The address is 24 bits long.

1 (32_BIT): The address is 32 bits long.

Bit 12 – TFRTYP: Data Transfer Type

Data Transfer Type

Value	Name	Description
0	TRSFR_READTRSFR_REGISTER	Read transfer from the serial memory. Scrambling is not performed. Read at random location (fetch) in the serial Flash memory is not possible.Read/Write transfer from the serial memory. Scrambling is not performed. Read at random location (fetch) in the serial Flash memory is not possible.
1	TRSFR_READ_MEMORYTRSFR_MEMORY	Read data transfer from the serial memory. If enabled, scrambling is performed. Read at random location (fetch) in the serial Flash memory is possible.Read/Write data transfer from the serial memory. If enabled, scrambling is performed. Read at random location (fetch) in the serial Flash memory is possible.
2	TRSFR_WRITE	Write transfer into the serial memory. Scrambling is not performed.
3	TRSFR_WRITE_MEMORY	Write data transfer into the serial memory. If enabled, scrambling is performed.

Bit 14 – CRM: Continuous Read Mode

Continuous Read Mode

0 (DISABLED): Continuous Read mode is disabled.

1 (ENABLED): Continuous Read mode is enabled.

Bit 15 – DDREN: DDR Mode Enable

DDR Mode Enable

0 (DISABLED): Transfers are performed in Single Data Rate mode.

1 (ENABLED): Transfers are performed in Double Data Rate mode, whereas the instruction field is still transferred in Single Data Rate mode.

Note: The DDRCMDEN bit defines how the instruction field is sent when Double Data Rate mode is enabled. If DDRCMDEN bit is at ‘0’, the instruction field is sent in Single Data Rate mode.

Bits 20:16 – NBDUM[4:0]: Number Of Dummy Cycles

Number Of Dummy Cycles

The NBDUM field defines the number of dummy cycles required by the serial Flash memory before data transfer.

Bit 24 – APBTFRTYP: APB Transfer Type

APB Transfer Type

Value	Description
0	APB register transfer to the memory is a write transfer. Useful when TRFTYP is written to ‘0’ and SMRM to ‘1’.
1	APB register transfer to the memory is a read transfer. Useful when TRFTYP is written to ‘0’ and SMRM to ‘1’.

Bit 26 – DDRCMDEN: DDR Mode Command Enable

DDR Mode Command Enable

0 (DISABLED): Transfer of instruction field is performed in Single Data Rate mode even if the DDREN bit is written to ‘1’.

1 (ENABLED): Transfer of instruction field is performed in Double Data Rate mode if the DDREN bit is written to ‘1’. If the DDREN bit is written to ‘0’, the instruction field is sent in Single Data Rate mode.