TC_EMRx

TC Extended Mode Register

This register can only be written if the WPEN bit is cleared in the TC Write Protection Mode Register.

  0x30 + x*0x40 [x=0..2] 32 Read/Write 0x00000000   3 64 -1
Parent topic: Register Summary

TC Extended Mode Register

Bit  31 30 29 28 27 26 25 24  
                   
Access                   
Reset                   
Bit  23 22 21 20 19 18 17 16  
                   
Access                   
Reset                   
Bit  15 14 13 12 11 10 9 8  
                NODIVCLK  
Access                R/W  
Reset                0  
Bit  7 6 5 4 3 2 1 0  
      TRIGSRCB[1:0]     TRIGSRCA[1:0]  
Access      R/W R/W     R/W R/W  
Reset      0 0     0 0  

Bits 1:0 – TRIGSRCA[1:0]: Trigger Source for Input A

Trigger Source for Input A

ValueNameDescription
0 EXTERNAL_TIOAx

The trigger/capture input A is driven by external pin TIOAx
1 PWMx

The trigger/capture input A is driven internally by PWMx

Bits 5:4 – TRIGSRCB[1:0]: Trigger Source for Input B

Trigger Source for Input B

ValueNameDescription
0 EXTERNAL_TIOBx The trigger/capture input B is driven by external pin TIOBx
1 PWMx For TC0 to TC10: The trigger/capture input B is driven internally by the comparator output (see Synchronization with PWM) of the PWMx.

For TC11: The trigger/capture input B is driven internally by the GTSUCOMP signal of the Ethernet MAC (GMAC).

Bit 8 – NODIVCLK: No Divided Clock

No Divided Clock

ValueDescription
0 The selected clock is defined by field TCCLKS in TC_CMRx.
1 The selected clock is peripheral clock and TCCLKS field (TC_CMRx) has no effect.