ISI Status Register
Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
FR_OVR | CRC_ERR | C_OVR | P_OVR | ||||||
Access | R | R | R | R | |||||
Reset | 0 | 0 | 0 | 0 |
Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
SIP | CXFR_DONE | PXFR_DONE | |||||||
Access | R | R | R | ||||||
Reset | 0 | 0 | 0 |
Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
VSYNC | CDC_PND | ||||||||
Access | R | R | |||||||
Reset | 0 | 0 |
Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
SRST | DIS_DONE | ENABLE | |||||||
Access | R | R | R | ||||||
Reset | 0 | 0 | 0 |
Module Enable
Value | Description |
---|---|
0 | Module is disabled. |
1 | Module is enabled. |
Module Disable Request has Terminated (cleared on read)
Value | Description |
---|---|
0 | Indicates that the request is not completed (if a request was issued). |
1 | Disable request has completed. This flag is reset after a read operation. |
Module Software Reset Request has Terminated (cleared on read)
Value | Description |
---|---|
0 | Indicates that the request is not completed (if a request was issued). |
1 | Software reset request has completed. This flag is reset after a read operation. |
Pending Codec Request
Value | Description |
---|---|
0 | Indicates that no codec request is pending |
1 | Indicates that the request has been taken into account but cannot be serviced within the current frame. The operation is postponed to the next frame. |
Vertical Synchronization (cleared on read)
Value | Description |
---|---|
0 | Indicates that the vertical synchronization has not been detected since the last read of the ISI_SR. |
1 | Indicates that a vertical synchronization has been detected since the last read of the ISI_SR. |
Preview DMA Transfer has Terminated (cleared on read)
Value | Description |
---|---|
0 | Preview transfer done not detected. |
1 | Preview transfer done detected. When set, this bit indicates that the data transfer on the preview channel has completed since the last read of ISI_SR. |
Codec DMA Transfer has Terminated (cleared on read)
Value | Description |
---|---|
0 | Codec transfer done not detected. |
1 | Codec transfer done detected. When set, this bit indicates that the data transfer on the codec channel has completed since the last read of ISI_SR. |
Synchronization in Progress
When the status of the preview or codec DMA channel is modified, a minimum amount of time is required to perform the clock domain synchronization.
Value | Description |
---|---|
0 | The clock domain synchronization process is terminated. |
1 | This bit is set when the clock domain synchronization operation occurs. No modification of the channel status is allowed when this bit is set, to guarantee data integrity. |
Preview Datapath Overflow (cleared on read)
Value | Description |
---|---|
0 | No overflow |
1 | An overrun condition has occurred in input FIFO on the preview path. The overrun happens when the FIFO is full and an attempt is made to write a new sample to the FIFO since the last read of ISI_SR. |
Codec Datapath Overflow (cleared on read)
Value | Description |
---|---|
0 | No overflow |
1 | An overrun condition has occurred in input FIFO on the codec path. The overrun happens when the FIFO is full and an attempt is made to write a new sample to the FIFO since the last read of ISI_SR. |
CRC Synchronization Error (cleared on read)
Value | Description |
---|---|
0 | No CRC error in the embedded synchronization frame (SAV/EAV) |
1 | Embedded Synchronization Correction is enabled (CRC_SYNC bit is set) in the ISI_CR and an error has been detected and not corrected since the last read of ISI_SR. The frame is discarded and the ISI waits for a new one. |
Frame Rate Overrun (cleared on read)
Value | Description |
---|---|
0 | No frame overrun |
1 | Frame overrun. The current frame is being skipped because a vsync signal has been detected while flushing FIFOs since the last read of ISI_SR. |