USART Interrupt Disable Register (SPI_MODE)
This configuration is relevant only if USART_MODE = 0xE or 0xF in the USART Mode Register.
The following configuration values are valid for all listed bit names of this register:
0: No effect
1: Disables the corresponding interrupt.
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| Access | |||||||||
| Reset |
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| NSSE | |||||||||
| Access | |||||||||
| Reset |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| UNRE | TXEMPTY | ||||||||
| Access | |||||||||
| Reset |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| OVRE | TXRDY | RXRDY | |||||||
| Access | |||||||||
| Reset |
RXRDY Interrupt Disable
TXRDY Interrupt Disable
Overrun Error Interrupt Disable
TXEMPTY Interrupt Disable
SPI Underrun Error Interrupt Disable
NSS Line (Driving CTS Pin) Rising or Falling Edge Event Interrupt Disable