MediaLB Channel Status1 Register
Each bit can be cleared by writing a 0.
Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
MCS: MediaLB Channel Status [63[31:24] | |||||||||
Access | |||||||||
Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
MCS: MediaLB Channel Status [63[23:16] | |||||||||
Access | |||||||||
Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
MCS: MediaLB Channel Status [63[15:8] | |||||||||
Access | |||||||||
Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
MCS: MediaLB Channel Status [63[7:0] | |||||||||
Access | |||||||||
Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
32] (cleared by writing a 0)
Indicates the channel status for MediaLB channels 63 to 32. Channel status bits are set by hardware and cleared by software. Status is only set if the appropriate bits in the MLB_MIEN register are set.