AFEC Interrupt Enable 1 Register
The following configuration values are valid for all listed bit names of this register:
0: No effect.
1: Enables the corresponding interrupt.
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| TEMPCHG | COMPE | GOVRE | DRDY | ||||||
| Access | W | W | W | W | |||||
| Reset | – | – | – | – |
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| Access | |||||||||
| Reset |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| EOC11 | EOC10 | EOC9 | EOC8 | ||||||
| Access | W | W | W | W | |||||
| Reset | – | – | – | – |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| EOC7 | EOC6 | EOC5 | EOC4 | EOC3 | EOC2 | EOC1 | EOC0 | ||
| Access | W | W | W | W | W | W | W | W | |
| Reset | – | – | – | – | – | – | – | – |
End of Conversion Interrupt Enable x
Data Ready Interrupt Enable
General Overrun Error Interrupt Enable
Comparison Event Interrupt Enable
Temperature Change Interrupt Enable