The receiver detects a break condition when all data, parity and stop bits are low. This corresponds to detecting a framing error with data to 0x00, but FRAME remains low.
When the low stop bit is detected, the receiver asserts US_CSR.RXBRK. This bit may be cleared by writing a ‘1’ to US_CR.RSTSTA.
An end of receive break is detected by a high level for at least 2/16 of a bit period in Asynchronous operating mode or one sample at high level in Synchronous operating mode. The end of break detection also asserts US_CSR.RXBRK bit.