Data Transmit with the DMA in Master Mode

The DMA transfer size must be defined with the buffer size minus 1. The remaining character must be managed without DMA to ensure that the exact number of bytes are transmitted regardless of system bus latency conditions during the end of the buffer transfer period.

  1. 1.Initialize the DMA (channels, memory pointers, size - 1, etc.);
  2. 2.Configure the Master mode (DADR, CKDIV, MREAD = 0, etc.) or Slave mode.
  3. 3.Enable the DMA.
  4. 4.Wait for the DMA status flag indicating that the buffer transfer is complete.
  5. 5.Disable the DMA.
  6. 6.Wait for the TXRDY flag in TWIHS_SR.
  7. 7.Set TWIHS_CR.STOP.
  8. 8.Write the last character in TWIHS_THR.
  9. 9.(Only if peripheral clock must be disabled) Wait for the TXCOMP flag to be raised in TWIHS_SR.
Parent topic: Using the DMA Controller (DMAC) in Master Mode