AES Interrupt Status Register
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| Access | |||||||||
| Reset |
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| TAGRDY | |||||||||
| Access | R | ||||||||
| Reset | 0 |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| URAT[3:0] | URAD | ||||||||
| Access | R | R | R | R | R | ||||
| Reset | 0 | 0 | 0 | 0 | 0 | ||||
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| DATRDY | |||||||||
| Access | R | ||||||||
| Reset | 0 |
Data Ready (cleared by setting bit START or bit SWRST in AES_CR or by reading AES_ODATARx)
| Value | Description |
|---|---|
| 0 | Output data not valid. |
| 1 | Encryption or decryption process is completed. |
Unspecified Register Access Detection Status (cleared by writing SWRST in AES_CR)
| Value | Description |
|---|---|
| 0 | No unspecified register access has been detected since the last SWRST. |
| 1 | At least one unspecified register access has been detected since the last SWRST. |
Unspecified Register Access (cleared by writing SWRST in AES_CR)
Only the last Unspecified Register Access Type is available through the URAT field.
| Value | Name | Description |
|---|---|---|
| 0 | IDR_WR_PROCESSING | Input Data register written during the data processing when SMOD = 2 mode. |
| 1 | ODR_RD_PROCESSING | Output Data register read during the data processing. |
| 2 | MR_WR_PROCESSING | Mode register written during the data processing. |
| 3 | ODR_RD_SUBKGEN | Output Data register read during the sub-keys generation. |
| 4 | MR_WR_SUBKGEN | Mode register written during the sub-keys generation. |
| 5 | WOR_RD_ACCESS | Write-only register read access. |
GCM Tag Ready
| Value | Description |
|---|---|
| 0 | GCM Tag is not valid. |
| 1 | GCM Tag generation is complete (cleared by reading GCM Tag, starting another processing or when writing a new key). |