TWIHS_IER

TWIHS Interrupt Enable Register

The following configuration values are valid for all listed bit names of this register:

0: No effect.

1: Enables the corresponding interrupt.

  0x24 32 Write-only –  
Parent topic: Register Summary

TWIHS Interrupt Enable Register

Bit  31 30 29 28 27 26 25 24  
                   
Access                   
Reset                   
Bit  23 22 21 20 19 18 17 16  
                   
Access                   
Reset                   
Bit  15 14 13 12 11 10 9 8  
          EOSACC SCL_WS ARBLST NACK  
Access          W W W W  
Reset          – – – –  
Bit  7 6 5 4 3 2 1 0  
  UNRE OVRE GACC SVACC   TXRDY RXRDY TXCOMP  
Access  W W W W   W W W  
Reset  – – – –   – – –  

Bit 0 – TXCOMP: Transmission Completed Interrupt Enable

Transmission Completed Interrupt Enable

Bit 1 – RXRDY: Receive Holding Register Ready Interrupt Enable

Receive Holding Register Ready Interrupt Enable

Bit 2 – TXRDY: Transmit Holding Register Ready Interrupt Enable

Transmit Holding Register Ready Interrupt Enable

Bit 4 – SVACC: Slave Access Interrupt Enable

Slave Access Interrupt Enable

Bit 5 – GACC: General Call Access Interrupt Enable

General Call Access Interrupt Enable

Bit 6 – OVRE: Overrun Error Interrupt Enable

Overrun Error Interrupt Enable

Bit 7 – UNRE: Underrun Error Interrupt Enable

Underrun Error Interrupt Enable

Bit 8 – NACK: Not Acknowledge Interrupt Enable

Not Acknowledge Interrupt Enable

Bit 9 – ARBLST: Arbitration Lost Interrupt Enable

Arbitration Lost Interrupt Enable

Bit 10 – SCL_WS: Clock Wait State Interrupt Enable

Clock Wait State Interrupt Enable

Bit 11 – EOSACC: End Of Slave Access Interrupt Enable

End Of Slave Access Interrupt Enable