If the chip select and the MSB of addresses as defined in Table 1 are identical, then the current access lies in the same page as the previous one, and no page break occurs.
Using this information, all data within the same page, sequential or not sequential, are accessed with a minimum access time (tsa). The following figure illustrates access to an 8-bit memory device in Page mode, with 8-byte pages. Access to D1 causes a page access with a long access time (tpa). Accesses to D3 and D7, though they are not sequential accesses, only require a short access time (tsa).
If the MSB of addresses are different, the SMC performs the access of a new page. In the same way, if the chip select is different from the previous access, a page break occurs. If two sequential accesses are made to the Page mode memory, but separated by an other internal or external peripheral access, a page break occurs on the second access because the chip select of the device was deasserted between both accesses.
