Memory Controllers

  Signal Name Recommended Pin Connection Description
External Bus Interface
  D[15:0] Application dependent. Data Bus (D0 to D15)

All data lines are pullup inputs to VDDIO at reset.

  A[23:0] Application dependent. Address Bus (A0 to A23)

All address lines pullup inputs to VDDIO at reset.

  NWAIT Application dependent. External Wait Signal.

Pulled-up input (100 kOhm) to VDDIO at reset.

Static Memory Controller
  NCS0-NCS3 Application dependent.

(Pullup at VDDIO)

Chip Select Lines

All are pulled-up inputs (100 kOhm) to VDDIO at reset.

  NRD Application dependent. Read Signal

Pulled-up input (100 kOhm) to VDDIO at reset.

  NWE Application dependent. Write Enable

All are pulled-up inputs (100 kOhm) to VDDIO at reset.

  NWR0–NWR1 Application dependent. Write Signals

All are pulled-up inputs (100 kOhm) to VDDIO at reset.

  NBS0–NBS1 Application dependent. Byte Mask Signals

All are pulled-up inputs (100 kOhm) to VDDIO at reset.

NAND Flash Logic
  NANDOE Application dependent. NAND Flash Output Enable

Pulled-up input (100 kOhm) to VDDIO at reset.

  NANDWE Application dependent. NAND Flash Write Enable

Pulled-up input (100 kOhm) to VDDIO at reset.

SDR-SDRAM Controller Logic
  SDCK Application dependent. SDRAM Clock

Pulled-up input (100 kOhm) to VDDIO at reset.

  SDCKE Application dependent. SDRAM Clock Enable

Pulled-up input (100 kOhm) to VDDIO at reset.

  SDCS Application dependent.

(Pullup at VDDIO)

SDRAM Controller Chip Select

Pulled-up input (100 kOhm) to VDDIO at reset.

  BA0–BA1 Application dependent. Bank Select

Pulled-up inputs (100 kOhm) to VDDIO at reset.

  SDWE Application dependent. SDRAM Write Enable

Pulled-up input (100 kOhm) to VDDIO at reset.

  RAS–CAS Application dependent. Row and Column Signal

Pulled-up inputs (100 kOhm) to VDDIO at reset.

  SDA10 Application dependent. SDRAM Address 10 Line

Pulled-up input (100 kOhm) to VDDIO at reset.

Figure 1. Schematic Example with a 16 Mb/16-bit SDRAM
Figure 2. Schematic Example with a 2 Gb/8-bit NAND Flash