Device Endpoint Register
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| EPRST9 | EPRST8 | ||||||||
| Access | |||||||||
| Reset | 0 | 0 |
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| EPRST7 | EPRST6 | EPRST5 | EPRST4 | EPRST3 | EPRST2 | EPRST1 | EPRST0 | ||
| Access | |||||||||
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| EPEN9 | EPEN8 | ||||||||
| Access | |||||||||
| Reset | 0 | 0 |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| EPEN7 | EPEN6 | EPEN5 | EPEN4 | EPEN3 | EPEN2 | EPEN1 | EPEN0 | ||
| Access | |||||||||
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
Endpoint x Enable
| Value | Description |
|---|---|
| 0 | Endpoint x is disabled, forcing the endpoint x state to inactive (no answer to USB requests) and resetting the endpoint x registers (USBHS_DEVEPTCFGx, USBHS_DEVEPTISRx, USBHS_DEVEPTIMRx) but not the endpoint configuration (USBHS_DEVEPTCFGx.ALLOC, USBHS_DEVEPTCFGx.EPBK, USBHS_DEVEPTCFGx.EPSIZE, USBHS_DEVEPTCFGx.EPDIR, USBHS_DEVEPTCFGx.EPTYPE). |
| 1 | Endpoint x is enabled. |
Endpoint x Reset
The whole endpoint mechanism (FIFO counter, reception, transmission, etc.) is reset apart from the Data Toggle Sequence field (USBHS_DEVEPTISRx.DTSEQ), which can be cleared by setting the USBHS_DEVEPTIMRx.RSTDT bit (by writing a one to the USBHS_DEVEPTIERx.RSTDTS bit).
The endpoint configuration remains active and the endpoint is still enabled.
This bit is cleared upon receiving a USB reset.
| Value | Description |
|---|---|
| 0 | Completes the reset operation and starts using the FIFO. |
| 1 | Resets the endpoint x FIFO prior to any other operation, upon hardware reset or when a USB bus reset has been received. This resets the endpoint x registers (USBHS_DEVEPTCFGx, USBHS_DEVEPTISRx, USBHS_DEVEPTIMRx) but not the endpoint configuration (USBHS_DEVEPTCFGx.ALLOC, USBHS_DEVEPTCFGx.EPBK, USBHS_DEVEPTCFGx.EPSIZE, USBHS_DEVEPTCFGx.EPDIR, USBHS_DEVEPTCFGx.EPTYPE). |