US_LINMR

USART LIN Mode Register

This register is relevant only if USART_MODE = 0xA or 0xB in the USART Mode Register.

  0x0054 32 Read/Write 0x0  
Parent topic: Register Summary

USART LIN Mode Register

Bit  31 30 29 28 27 26 25 24  
                   
Access                   
Reset                   
Bit  23 22 21 20 19 18 17 16  
              SYNCDIS PDCM  
Access                   
Reset              0 0  
Bit  15 14 13 12 11 10 9 8  
  DLC[7:0]  
Access                   
Reset  0 0 0 0 0 0 0 0  
Bit  7 6 5 4 3 2 1 0  
  WKUPTYP FSDIS DLM CHKTYP CHKDIS PARDIS NACT[1:0]  
Access                   
Reset  0 0 0 0 0 0 0 0  

Bits 1:0 – NACT[1:0]: LIN Node Action

LIN Node Action

Values which are not listed in the table must be considered as “reserved”.

ValueNameDescription
00 PUBLISH

The USART transmits the response.
01 SUBSCRIBE

The USART receives the response.
10 IGNORE

The USART does not transmit and does not receive the response.

Bit 2 – PARDIS: Parity Disable

Parity Disable

ValueDescription
0

In master node configuration, the identifier parity is computed and sent automatically. In master node and slave node configuration, the parity is checked automatically.
1

Whatever the node configuration is, the Identifier parity is not computed/sent and it is not checked.

Bit 3 – CHKDIS: Checksum Disable

Checksum Disable

ValueDescription
0

In master node configuration, the checksum is computed and sent automatically. In slave node configuration, the checksum is checked automatically.
1

Whatever the node configuration is, the checksum is not computed/sent and it is not checked.

Bit 4 – CHKTYP: Checksum Type

Checksum Type

ValueDescription
0

LIN 2.0 “enhanced” checksum
1

LIN 1.3 “classic” checksum

Bit 5 – DLM: Data Length Mode

Data Length Mode

ValueDescription
0

The response data length is defined by field DLC of this register.
1

The response data length is defined by bits 5 and 6 of the identifier (IDCHR in US_LINIR).

Bit 6 – FSDIS: Frame Slot Mode Disable

Frame Slot Mode Disable

ValueDescription
0

The Frame Slot mode is enabled.
1

The Frame Slot mode is disabled.

Bit 7 – WKUPTYP: Wakeup Signal Type

Wakeup Signal Type

ValueDescription
0

Setting the bit LINWKUP in US_CR sends a LIN 2.0 wakeup signal.
1

Setting the bit LINWKUP in US_CR sends a LIN 1.3 wakeup signal.

Bits 15:8 – DLC[7:0]: Data Length Control

Data Length Control

ValueDescription
0–255

Defines the response data length if DLM = 0,in that case the response data length is equal to DLC+1 bytes.

Bit 16 – PDCM: DMAC Mode

DMAC Mode

ValueDescription
0

The LIN mode register US_LINMR is not written by the DMAC.
1

The LIN mode register US_LINMR (excepting that flag) is written by the DMAC.

Bit 17 – SYNCDIS: Synchronization Disable

Synchronization Disable

ValueDescription
0

The synchronization procedure is performed in LIN slave node configuration.
1

The synchronization procedure is not performed in LIN slave node configuration.