MCAN_CREL

MCAN Core Release Register

Due to clock domain crossing, there is a delay between when a register bit or field is written and when the related status register bits are updated.
Note: For revision A silicon the reset value is 0x30130506.
  0x00 32 Read-only 0x32150320  
Parent topic: Register Summary

MCAN Core Release Register

Bit  31 30 29 28 27 26 25 24  
  REL[3:0] STEP[3:0]  
Access  R R R R R R R R  
Reset  x x x x x x x x  
Bit  23 22 21 20 19 18 17 16  
  SUBSTEP[3:0] YEAR[3:0]  
Access  R R R R R R R R  
Reset  x x x x x x x x  
Bit  15 14 13 12 11 10 9 8  
  MON[7:0]  
Access  R R R R R R R R  
Reset  x x x x x x x x  
Bit  7 6 5 4 3 2 1 0  
  DAY[7:0]  
Access  R R R R R R R R  
Reset  x x x x x x x x  

Bits 7:0 – DAY[7:0]: Timestamp Day

Timestamp Day

Two digits, BCD-coded. This field is set by generic parameter on MCAN synthesis.

Bits 15:8 – MON[7:0]: Timestamp Month

Timestamp Month

Two digits, BCD-coded. This field is set by generic parameter on MCAN synthesis.

Bits 19:16 – YEAR[3:0]: Timestamp Year

Timestamp Year

One digit, BCD-coded. This field is set by generic parameter on MCAN synthesis.

Bits 23:20 – SUBSTEP[3:0]: Sub-step of Core Release

Sub-step of Core Release

One digit, BCD-coded.

Bits 27:24 – STEP[3:0]: Step of Core Release

Step of Core Release

One digit, BCD-coded.

Bits 31:28 – REL[3:0]: Core Release

Core Release

One digit, BCD-coded.