DACC Analog Current Register
This register can only be written if the WPEN bit is cleared in the DACC Write Protection Mode Register.
Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
Access | |||||||||
Reset |
Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
Access | |||||||||
Reset |
Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
Access | |||||||||
Reset |
Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
IBCTLCH1[1:0] | IBCTLCH0[1:0] | ||||||||
Access | R/W | R/W | R/W | R/W | |||||
Reset | 0 | 0 | 0 | 0 |
Analog Output Current Control
Allows to adapt the slew rate of the analog output. For more details, refer to the DAC Characteristics in the section “Electrical Characteristics” of this datasheet.