Register Summary

Note: Several parts of the ISI controller use the pixel clock provided by the image sensor (ISI_PCK). Thus the user must first program the image sensor to provide this clock (ISI_PCK) before programming the Image Sensor Controller.
Offset Name Bit Pos. 7 6 5 4 3 2 1 0
0x00 ISI_CFG1 7:0 CRC_SYNC EMB_SYNC GRAYLE PIXCLK_POL VSYNC_POL HSYNC_POL    
15:8   THMASK[1:0] FULL DISCR FRATE[2:0]
23:16 SLD[7:0]
31:24 SFD[7:0]
0x04 ISI_CFG2 7:0 IM_VSIZE[7:0]
15:8 COL_SPACE RGB_SWAP GRAYSCALE RGB_MODE GS_MODE IM_VSIZE[10:8]
23:16 IM_HSIZE[7:0]
31:24 RGB_CFG[1:0] YCC_SWAP[1:0]   IM_HSIZE[10:8]
0x08 ISI_PSIZE 7:0 PREV_VSIZE[7:0]
15:8             PREV_VSIZE[9:8]
23:16 PREV_HSIZE[7:0]
31:24             PREV_HSIZE[9:8]
0x0C ISI_PDECF 7:0 DEC_FACTOR[7:0]
15:8                
23:16                
31:24                
0x10 ISI_Y2R_SET0 7:0 C0[7:0]
15:8 C1[7:0]
23:16 C2[7:0]
31:24 C3[7:0]
0x14 ISI_Y2R_SET1 7:0 C4[7:0]
15:8   Cboff Croff Yoff       C4[8]
23:16                
31:24                
0x18 ISI_R2Y_SET0 7:0   C0[6:0]
15:8   C1[6:0]
23:16   C2[6:0]
31:24               Roff
0x1C ISI_R2Y_SET1 7:0   C3[6:0]
15:8   C4[6:0]
23:16   C5[6:0]
31:24               Goff
0x20 ISI_R2Y_SET2 7:0   C6[6:0]
15:8   C7[6:0]
23:16   C8[6:0]
31:24               Boff
0x24 ISI_CR 7:0           ISI_SRST ISI_DIS ISI_EN
15:8               ISI_CDC
23:16                
31:24                
0x28 ISI_SR 7:0           SRST DIS_DONE ENABLE
15:8           VSYNC   CDC_PND
23:16         SIP   CXFR_DONE PXFR_DONE
31:24         FR_OVR CRC_ERR C_OVR P_OVR
0x2C ISI_IER 7:0           SRST DIS_DONE  
15:8           VSYNC    
23:16             CXFR_DONE PXFR_DONE
31:24         FR_OVR CRC_ERR C_OVR P_OVR
0x30 ISI_IDR 7:0           SRST DIS_DONE  
15:8           VSYNC    
23:16             CXFR_DONE PXFR_DONE
31:24         FR_OVR CRC_ERR C_OVR P_OVR
0x34 ISI_IMR 7:0           SRST DIS_DONE  
15:8           VSYNC    
23:16             CXFR_DONE PXFR_DONE
31:24         FR_OVR CRC_ERR C_OVR P_OVR
0x38 ISI_DMA_CHER 7:0             C_CH_EN P_CH_EN
15:8                
23:16                
31:24                
0x3C ISI_DMA_CHDR 7:0             C_CH_DIS P_CH_DIS
15:8                
23:16                
31:24                
0x40 ISI_DMA_CHSR 7:0             C_CH_S P_CH_S
15:8                
23:16                
31:24                
0x44 ISI_DMA_P_ADDR 7:0 P_ADDR[5:0]    
15:8 P_ADDR[13:6]
23:16 P_ADDR[21:14]
31:24 P_ADDR[29:22]
0x48 ISI_DMA_P_CTRL 7:0         P_DONE P_IEN P_WB P_FETCH
15:8                
23:16                
31:24                
0x4C ISI_DMA_P_DSCR 7:0 P_DSCR[5:0]    
15:8 P_DSCR[13:6]
23:16 P_DSCR[21:14]
31:24 P_DSCR[29:22]
0x50 ISI_DMA_C_ADDR 7:0 C_ADDR[5:0]    
15:8 C_ADDR[13:6]
23:16 C_ADDR[21:14]
31:24 C_ADDR[29:22]
0x54 ISI_DMA_C_CTRL 7:0         C_DONE C_IEN C_WB C_FETCH
15:8                
23:16                
31:24                
0x58 ISI_DMA_C_DSCR 7:0 C_DSCR[5:0]    
15:8 C_DSCR[13:6]
23:16 C_DSCR[21:14]
31:24 C_DSCR[29:22]

0x5C

...

0xE3

 Reserved                  
0xE4 ISI_WPMR 7:0               WPEN
15:8 WPKEY[7:0]
23:16 WPKEY[15:8]
31:24 WPKEY[23:16]
0xE8 ISI_WPSR 7:0               WPVS
15:8 WPVSRC[7:0]
23:16 WPVSRC[15:8]
31:24