UART Status Register
Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
Access | |||||||||
Reset |
Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
Access | |||||||||
Reset |
Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
CMP | TXEMPTY | ||||||||
Access | R | R | |||||||
Reset | 0 | 0 |
Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
PARE | FRAME | OVRE | TXRDY | RXRDY | |||||
Access | R | R | R | R | R | ||||
Reset | 0 | 0 | 0 | 0 | 0 |
Receiver Ready
Value | Description |
---|---|
0 | No character has been received since the last read of the UART_RHR, or the receiver is disabled. |
1 | At least one complete character has been received, transferred to UART_RHR and not yet read. |
Transmitter Ready
Value | Description |
---|---|
0 | A character has been written to UART_THR and not yet transferred to the internal shift register, or the transmitter is disabled. |
1 | There is no character written to UART_THR not yet transferred to the internal shift register. |
Overrun Error
Value | Description |
---|---|
0 | No overrun error has occurred since the last RSTSTA. |
1 | At least one overrun error has occurred since the last RSTSTA. |
Framing Error
Value | Description |
---|---|
0 | No framing error has occurred since the last RSTSTA. |
1 | At least one framing error has occurred since the last RSTSTA. |
Parity Error
Value | Description |
---|---|
0 | No parity error has occurred since the last RSTSTA. |
1 | At least one parity error has occurred since the last RSTSTA. |
Transmitter Empty
Value | Description |
---|---|
0 | There are characters in UART_THR, or characters being processed by the transmitter, or the transmitter is disabled. |
1 | There are no characters in UART_THR and there are no characters being processed by the transmitter. |
Comparison Match
Value | Description |
---|---|
0 | No received character matches the comparison criteria programmed in VAL1, VAL2 fields and in CMPPAR bit since the last RSTSTA. |
1 | The received character matches the comparison criteria. |