GMAC_TUR

GMAC Transmit Underruns Register

  0x134 32 - 0x00000000  

GMAC Transmit Underruns Register

Bit  31 30 29 28 27 26 25 24  
                   
Access                   
Reset                   
Bit  23 22 21 20 19 18 17 16  
                   
Access                   
Reset                   
Bit  15 14 13 12 11 10 9 8  
              TXUNR[9:8]  
Access              R R  
Reset              0 0  
Bit  7 6 5 4 3 2 1 0  
  TXUNR[7:0]  
Access  R R R R R R R R  
Reset  0 0 0 0 0 0 0 0  

Bits 9:0 – TXUNR[9:0]: Transmit Underruns

Transmit Underruns

This register counts the number of frames not transmitted due to a transmit underrun. If this register is incremented then no other statistics register is incremented.