To perform conversions, the DACC_CHSR.CHx bit must be set by writing a one to DACC_CHER.CHx. If both DACC_CHSR.CHx bits are cleared, the DAC analog cell is switched off. The DACx is ready to convert once DACC_CHSR.DACRDYx is read at ‘1’.
The DACC divides the peripheral clock to perform conversions. This divided clock is named DAC clock. Once a conversion starts, the DACC takes 12 DAC clock periods to provide the analog result on the selected analog output.
The minimum conversion period of the DAC is exactly 12 DAC clock periods when the Max speed mode is enabled (MAXSx = 1 in the DACC Mode Register (DACC_MR)). In this case the DAC is always clocked, slightly increasing the power consumption of the DAC.
When the Max speed mode is not used (Trigger or Free-running mode), the DAC is only clocked when a conversion is requested and a new conversion can only occur when the DAC has ended its previous conversion. The power consumption is lower but the sampling rate is lower as the controller waits for the end of conversion of the previously sent data. In this case, one conversion lasts 12 DAC clock periods plus 2 cycles of resynchronization stage.
The conversion mode of a channel can be modified only if this channel has been previously disabled.
Power consumption of the DAC can be adapted to its sampling rate via the DACC_ACR.IBCTLCHx fields.
In Bypass mode, the maximum sample rate and the power consumption of the DAC are lowered.