GMAC_NCR

GMAC Network Control Register

  0x000 32 Read/Write 0x00000000  
Parent topic: Register Summary

GMAC Network Control Register

Bit  31 30 29 28 27 26 25 24  
                   
Access                   
Reset                   
Bit  23 22 21 20 19 18 17 16  
            FNP TXPBPF ENPBPR  
Access            R/W R/W R/W  
Reset            0 0 0  
Bit  15 14 13 12 11 10 9 8  
  SRTSM     TXZQPF TXPF THALT TSTART BP  
Access  R/W     R/W R/W R/W R/W R/W  
Reset  0     0 0 0 0 0  
Bit  7 6 5 4 3 2 1 0  
  WESTAT INCSTAT CLRSTAT MPE TXEN RXEN LBL    
Access  R/W R/W R/W R/W R/W R/W R/W    
Reset  0 0 0 0 0 0 0    

Bit 1 – LBL: Loop Back Local

Loop Back Local

Writing '1' to this bit connects GTX to GRX, GTXEN to GRXDV, and forces full duplex mode.

GRXCK and GTXCK may malfunction as the GMAC is switched into and out of internal loop back. It is important that receive and transmit circuits have already been disabled when making the switch into and out of internal loop back.

ValueDescription
0 Loop back local is disabled.
1 Loop back local is enabled.

Bit 2 – RXEN: Receive Enable

Receive Enable

Writing a '1' to this bit enables the GMAC to receive data.

Writing a '0' to this bit stops frame reception immediately, and the receive pipeline is cleared. The Receive Queue Pointer Register is not affected.

ValueDescription
0 Receive is disabled.
1 Receive is enabled.

Bit 3 – TXEN: Transmit Enable

Transmit Enable

Writing a '1' to this bit enables the GMAC transmitter to send data.

Writing a '0' to this bit stops transmission immediately, the transmit pipeline and control registers is cleared, and the Transmit Queue Pointer Register will be set to point to the start of the transmit descriptor list.

ValueDescription
0 Transmit is disabled.
1 Transmit is enabled.

Bit 4 – MPE: Management Port Enable

Management Port Enable

Writing a '1' to this bit enables the Management Port.

Writing a '0' to this bit disables the Management Port, and forces MDIO to high impedance state and MDC to low impedance.

ValueDescription
0 Management Port is disabled.
1 Management Port is enabled.

Bit 5 – CLRSTAT: Clear Statistics Registers

Clear Statistics Registers

Writing a '1' to this bit clears the Statistics Registers.

Writing a '0' to this bit has no effect.

This bit will always read '0'.

Bit 6 – INCSTAT: Increment Statistics Registers

Increment Statistics Registers

Writing a '1' to this bit increments all Statistics Registers by one for test purposes.

Writing a '0' to this bit has no effect.

This bit will always read '0'.

Bit 7 – WESTAT: Write Enable for Statistics Registers

Write Enable for Statistics Registers

Writing a '1' to this bit makes the statistics registers writable for functional test purposes.

ValueDescription
0 Statistics Registers are write-protected.
1 Statistics Registers are write-enabled.

Bit 8 – BP: Back Pressure

Back Pressure

In 10M or 100M half duplex mode, writing a '1' to this bit forces collisions on all received frames. Ignored in gigabit half duplex mode.

ValueDescription
0 Frame collisions are not forced.
1 Frame collisions are forced in 10M and 100M half duplex mode.

Bit 9 – TSTART: Start Transmission

Start Transmission

Writing a '1' to this bit starts transmission.

Writing a '0' to this bit has no effect.

Bit 10 – THALT: Transmit Halt

Transmit Halt

Writing a '1' to this bit halts transmission as soon as any ongoing frame transmission ends.

Writing a '0' to this bit has no effect.

Bit 11 – TXPF: Transmit Pause Frame

Transmit Pause Frame

Writing one to this bit causes a pause frame to be transmitted.

Writing a '0' to this bit has no effect.

Bit 12 – TXZQPF: Transmit Zero Quantum Pause Frame

Transmit Zero Quantum Pause Frame

Writing a '1' to this bit causes a pause frame with zero quantum to be transmitted.

Writing a '0' to this bit has no effect.

Bit 15 – SRTSM: Store Receive Time Stamp to Memory

Store Receive Time Stamp to Memory

Writing a '1' to this bit causes the CRC of every received frame to be replaced with the value of the nanoseconds field of the 1588 timer that was captured as the receive frame passed the message time stamp point.

Note that bit RFCS in register GMAC_NCFGR may not be set to 1 when the timer should be captured.

ValueDescription
0 Normal operation
1 All received frames' CRC is replaced with a time stamp.

Bit 16 – ENPBPR: Enable PFC Priority-based Pause Reception

Enable PFC Priority-based Pause Reception

Writing a '1' to this bit enables PFC Priority Based Pause Reception capabilities, enabling PFC negotiation and recognition of priority-based pause frames.

ValueDescription
0 Normal operation
1 PFC Priority-based Pause frames are recognized.

Bit 17 – TXPBPF: Transmit PFC Priority-based Pause Frame

Transmit PFC Priority-based Pause Frame

Takes the values stored in the Transmit PFC Pause Register.

Bit 18 – FNP: Flush Next Packet

Flush Next Packet

Writing a '1' to this bit will flush the next packet from the external RX DPRAM. Flushing the next packet will only take effect if the DMA is not currently writing a packet already stored in the DPRAM to memory.