USART Interrupt Enable Register
For SPI specific configuration, see “USART Interrupt Enable Register (SPI_MODE)”.
For LIN specific configuration, see “USART Interrupt Enable Register (LIN_MODE)”.
For LON specific configuration, see “USART Interrupt Enable Register (LON_MODE)”.
The following configuration values are valid for all listed bit names of this register:
0: No effect
1: Enables the corresponding interrupt.
Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
Access | |||||||||
Reset |
Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
MANE | CTSIC | DCDIC | DSRIC | RIIC | |||||
Access | |||||||||
Reset |
Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
NACK | ITER | TXEMPTY | TIMEOUT | ||||||
Access | |||||||||
Reset |
Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
PARE | FRAME | OVRE | RXBRK | TXRDY | RXRDY | ||||
Access | |||||||||
Reset |
RXRDY Interrupt Enable
TXRDY Interrupt Enable
Receiver Break Interrupt Enable
Overrun Error Interrupt Enable
Framing Error Interrupt Enable
Parity Error Interrupt Enable
Timeout Interrupt Enable
TXEMPTY Interrupt Enable
Max number of Repetitions Reached Interrupt Enable
Non Acknowledge Interrupt Enable
Ring Indicator Input Change Enable
Data Set Ready Input Change Enable
Data Carrier Detect Input Change Interrupt Enable
Clear to Send Input Change Interrupt Enable
Manchester Error Interrupt Enable