DACC_IDR

DACC Interrupt Disable Register

The following configuration values are valid for all listed bit names of this register:

0: No effect.

1: Disables the corresponding interrupt.

  0x28 32 Write-only –  

DACC Interrupt Disable Register

Bit  31 30 29 28 27 26 25 24  
                   
Access                   
Reset                   
Bit  23 22 21 20 19 18 17 16  
                   
Access                   
Reset                   
Bit  15 14 13 12 11 10 9 8  
                   
Access                   
Reset                   
Bit  7 6 5 4 3 2 1 0  
      EOC1 EOC0     TXRDY1 TXRDY0  
Access      W W     W W  
Reset      0     0  

Bits 0, 1 – TXRDYx: Transmit Ready Interrupt Disable of channel x

Transmit Ready Interrupt Disable of channel x

Bits 4, 5 – EOCx: End of Conversion Interrupt Disable of channel x

End of Conversion Interrupt Disable of channel x