GMAC_IDRPQx

GMAC Interrupt Disable Register Priority Queue x

The following values are valid for all listed bit names of this register:

0: No effect.

1: Disables the corresponding interrupt.

  0x0620 + (x-1)*0x04 [x=1..5] 32 Write-only –   5 1index -1
Parent topic: Register Summary

GMAC Interrupt Disable Register Priority Queue x

Bit  31 30 29 28 27 26 25 24  
                   
Access                   
Reset                   
Bit  23 22 21 20 19 18 17 16  
                   
Access                   
Reset                   
Bit  15 14 13 12 11 10 9 8  
          HRESP ROVR      
Access          W W      
Reset          – –      
Bit  7 6 5 4 3 2 1 0  
  TCOMP TFC RLEX     RXUBR RCOMP    
Access  W W W     W W    
Reset  – – –     – –    

Bit 1 – RCOMP: Receive Complete

Receive Complete

Bit 2 – RXUBR: RX Used Bit Read

RX Used Bit Read

Bit 5 – RLEX: Retry Limit Exceeded or Late Collision

Retry Limit Exceeded or Late Collision

Bit 6 – TFC: Transmit Frame Corruption Due to AHB Error

Transmit Frame Corruption Due to AHB Error

Bit 7 – TCOMP: Transmit Complete

Transmit Complete

Bit 10 – ROVR: Receive Overrun

Receive Overrun

Bit 11 – HRESP: HRESP Not OK

HRESP Not OK