HSMCI Interrupt Mask Register
The following configuration values are valid for all listed bit names of this register:
0: The corresponding interrupt is not enabled.
1: The corresponding interrupt is enabled.
Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
UNRE | OVRE | ACKRCVE | ACKRCV | XFRDONE | FIFOEMPTY | BLKOVRE | |||
Access | |||||||||
Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
CSTOE | DTOE | DCRCE | RTOE | RENDE | RCRCE | RDIRE | RINDE | ||
Access | |||||||||
Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
CSRCV | SDIOWAIT | SDIOIRQA | |||||||
Access | |||||||||
Reset | 0 | 0 | 0 |
Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
NOTBUSY | DTIP | BLKE | TXRDY | RXRDY | CMDRDY | ||||
Access | |||||||||
Reset | 0 | 0 | 0 | 0 | 0 | 0 |
Command Ready Interrupt Mask
Receiver Ready Interrupt Mask
Transmit Ready Interrupt Mask
Data Block Ended Interrupt Mask
Data Transfer in Progress Interrupt Mask
Data Not Busy Interrupt Mask
SDIO Interrupt for Slot A Interrupt Mask
SDIO Read Wait Operation Status Interrupt Mask
Completion Signal Received Interrupt Mask
Response Index Error Interrupt Mask
Response Direction Error Interrupt Mask
Response CRC Error Interrupt Mask
Response End Bit Error Interrupt Mask
Response Time-out Error Interrupt Mask
Data CRC Error Interrupt Mask
Data Time-out Error Interrupt Mask
Completion Signal Time-out Error Interrupt Mask
DMA Block Overrun Error Interrupt Mask
FIFO Empty Interrupt Mask
Transfer Done Interrupt Mask
Boot Operation Acknowledge Received Interrupt Mask
Boot Operation Acknowledge Error Interrupt Mask
Overrun Interrupt Mask
Underrun Interrupt Mask