QSPI_SR

QSPI Status Register

  0x10 32 Read-only 0x00000000  
Parent topic: Register Summary

QSPI Status Register

Bit  31 30 29 28 27 26 25 24  
                QSPIENS  
Access                R  
Reset                0  
Bit  23 22 21 20 19 18 17 16  
                   
Access                   
Reset                   
Bit  15 14 13 12 11 10 9 8  
            INSTRE CSS CSR  
Access            R R R  
Reset            0 0 0  
Bit  7 6 5 4 3 2 1 0  
          OVRES TXEMPTY TDRE RDRF  
Access          R R R R  
Reset          0 0 0 0  

Bit 0 – RDRF: Receive Data Register Full (cleared by reading QSPI_RDR)

Receive Data Register Full (cleared by reading QSPI_RDR)

ValueDescription
0

No data has been received since the last read of QSPI_RDR.
1

Data has been received and the received data has been transferred from the serializer to QSPI_RDR since the last read of QSPI_RDR.

Bit 1 – TDRE: Transmit Data Register Empty (cleared by writing QSPI_TDR)

Transmit Data Register Empty (cleared by writing QSPI_TDR)

TDRE equals zero when the QSPI is disabled or at reset. The QSPI enable command sets this bit to one.

ValueDescription
0

Data has been written to QSPI_TDR and not yet transferred to the serializer.
1

The last data written in the QSPI_TDR has been transferred to the serializer.

Bit 2 – TXEMPTY: Transmission Registers Empty (cleared by writing QSPI_TDR)

Transmission Registers Empty (cleared by writing QSPI_TDR)

ValueDescription
0

As soon as data is written in QSPI_TDR.
1

QSPI_TDR and the internal shifter are empty. If a transfer delay has been defined, TXEMPTY is set after the completion of such delay.

Bit 3 – OVRES: Overrun Error Status (cleared on read)

Overrun Error Status (cleared on read)

An overrun occurs when QSPI_RDR is loaded at least twice from the serializer since the last read of the QSPI_RDR.

ValueDescription
0

No overrun has been detected since the last read of QSPI_SR.
1

At least one overrun error has occurred since the last read of QSPI_SR.

Bit 8 – CSR: Chip Select Rise (cleared on read)

Chip Select Rise (cleared on read)

ValueDescription
0

No chip select rise has been detected since the last read of QSPI_SR.
1

At least one chip select rise has been detected since the last read of QSPI_SR.

Bit 9 – CSS: Chip Select Status

Chip Select Status

ValueDescription
0

The chip select is asserted.
1

The chip select is not asserted.

Bit 10 – INSTRE: Instruction End Status (cleared on read)

Instruction End Status (cleared on read)

ValueDescription
0

No instruction end has been detected since the last read of QSPI_SR.
1

At least one instruction end has been detected since the last read of QSPI_SR.

Bit 24 – QSPIENS: QSPI Enable Status

QSPI Enable Status

ValueDescription
0

QSPI is disabled.
1

QSPI is enabled.