TC_CMRx

TC Channel Mode Register: Waveform Mode

This register can only be written if the WPEN bit is cleared in the TC Write Protection Mode Register.

  0x04 + x*0x40 [x=0..2] 32 Read/Write 0x00000000   3 64 -1

TC Channel Mode Register: Waveform Mode

Bit  31 30 29 28 27 26 25 24  
  BSWTRG[1:0] BEEVT[1:0] BCPC[1:0] BCPB[1:0]  
Access  R/W R/W R/W R/W R/W R/W R/W R/W  
Reset  0 0 0 0 0 0 0 0  
Bit  23 22 21 20 19 18 17 16  
  ASWTRG[1:0] AEEVT[1:0] ACPC[1:0] ACPA[1:0]  
Access  R/W R/W R/W R/W R/W R/W R/W R/W  
Reset  0 0 0 0 0 0 0 0  
Bit  15 14 13 12 11 10 9 8  
  WAVE WAVSEL[1:0] ENETRG EEVT[1:0] EEVTEDG[1:0]  
Access  R/W R/W R/W R/W R/W R/W R/W R/W  
Reset  0 0 0 0 0 0 0 0  
Bit  7 6 5 4 3 2 1 0  
  CPCDIS CPCSTOP BURST[1:0] CLKI TCCLKS[2:0]  
Access  R/W R/W R/W R/W R/W R/W R/W R/W  
Reset  0 0 0 0 0 0 0 0  

Bits 2:0 – TCCLKS[2:0]: Clock Selection

Clock Selection

To operate at maximum peripheral clock frequency, refer to “TC Extended Mode Register”.

ValueNameDescription
0 TIMER_CLOCK1 Clock selected: internal PCK6 or PCK7 (TC0 only) clock signal (from PMC)
1 TIMER_CLOCK2 Clock selected: internal MCK/8 clock signal (from PMC)
2 TIMER_CLOCK3 Clock selected: internal MCK/32 clock signal (from PMC)
3 TIMER_CLOCK4 Clock selected: internal MCK/128 clock signal (from PMC)
4 TIMER_CLOCK5 Clock selected: internal SLCK clock signal (from PMC)
5 XC0 Clock selected: XC0
6 XC1 Clock selected: XC1
7 XC2 Clock selected: XC2

Bit 3 – CLKI: Clock Invert

Clock Invert

ValueDescription
0 Counter is incremented on rising edge of the clock.
1 Counter is incremented on falling edge of the clock.

Bits 5:4 – BURST[1:0]: Burst Signal Selection

Burst Signal Selection

ValueNameDescription
0 NONE The clock is not gated by an external signal.
1 XC0 XC0 is ANDed with the selected clock.
2 XC1 XC1 is ANDed with the selected clock.
3 XC2 XC2 is ANDed with the selected clock.

Bit 6 – CPCSTOP: Counter Clock Stopped with RC Compare

Counter Clock Stopped with RC Compare

ValueDescription
0 Counter clock is not stopped when counter reaches RC.
1 Counter clock is stopped when counter reaches RC.

Bit 7 – CPCDIS: Counter Clock Disable with RC Compare

Counter Clock Disable with RC Compare

ValueDescription
0 Counter clock is not disabled when counter reaches RC.
1 Counter clock is disabled when counter reaches RC.

Bits 9:8 – EEVTEDG[1:0]: External Event Edge Selection

External Event Edge Selection

ValueNameDescription
0 NONE None
1 RISING Rising edge
2 FALLING Falling edge
3 EDGE Each edge

Bits 11:10 – EEVT[1:0]: External Event Selection

External Event Selection

Signal selected as external event.

Value Name Description TIOB Direction
0 TIOB TIOB Input
1 XC0 XC0 Output
2 XC1 XC1 Output
3 XC2 XC2 Output
Note: If TIOB is chosen as the external event signal, it is configured as an input and no longer generates waveforms and subsequently no IRQs.

Bit 12 – ENETRG: External Event Trigger Enable

External Event Trigger Enable

Whatever the value programmed in ENETRG, the selected external event only controls the TIOAx output and TIOBx if not used as input (trigger event input or other input used).
ValueDescription
0 The external event has no effect on the counter and its clock.
1 The external event resets the counter and starts the counter clock.

Bits 14:13 – WAVSEL[1:0]: Waveform Selection

Waveform Selection

ValueNameDescription
0 UP UP mode without automatic trigger on RC Compare
1 UPDOWN UPDOWN mode without automatic trigger on RC Compare
2 UP_RC UP mode with automatic trigger on RC Compare
3 UPDOWN_RC UPDOWN mode with automatic trigger on RC Compare

Bit 15 – WAVE: Waveform Mode

Waveform Mode

ValueDescription
0 Waveform mode is disabled (Capture mode is enabled).
1 Waveform mode is enabled.

Bits 17:16 – ACPA[1:0]: RA Compare Effect on TIOAx

RA Compare Effect on TIOAx

ValueNameDescription
0 NONE None
1 SET Set
2 CLEAR Clear
3 TOGGLE Toggle

Bits 19:18 – ACPC[1:0]: RC Compare Effect on TIOAx

RC Compare Effect on TIOAx

ValueNameDescription
0 NONE None
1 SET Set
2 CLEAR Clear
3 TOGGLE Toggle

Bits 21:20 – AEEVT[1:0]: External Event Effect on TIOAx

External Event Effect on TIOAx

ValueNameDescription
0 NONE None
1 SET Set
2 CLEAR Clear
3 TOGGLE Toggle

Bits 23:22 – ASWTRG[1:0]: Software Trigger Effect on TIOAx

Software Trigger Effect on TIOAx

ValueNameDescription
0 NONE None
1 SET Set
2 CLEAR Clear
3 TOGGLE Toggle

Bits 25:24 – BCPB[1:0]: RB Compare Effect on TIOBx

RB Compare Effect on TIOBx

ValueNameDescription
0 NONE

None

1 SET

Set

2 CLEAR

Clear

3 TOGGLE

Toggle

Bits 27:26 – BCPC[1:0]: RC Compare Effect on TIOBx

RC Compare Effect on TIOBx

ValueNameDescription
0 NONE

None

1 SET

Set

2 CLEAR

Clear

3 TOGGLE

Toggle

Bits 29:28 – BEEVT[1:0]: External Event Effect on TIOBx

External Event Effect on TIOBx

ValueNameDescription
0 NONE

None

1 SET

Set

2 CLEAR

Clear

3 TOGGLE

Toggle

Bits 31:30 – BSWTRG[1:0]: Software Trigger Effect on TIOBx

Software Trigger Effect on TIOBx

ValueNameDescription
0 NONE

None

1 SET

Set

2 CLEAR

Clear

3 TOGGLE

Toggle