The sequence of actions is as follows:
- 1.Write AES_MR with all required fields, including but not limited to SMOD and
OPMOD.
- 2.Write the 128-bit/192-bit/256-bit AES key in AES_KEYWRx.
- 3.Write the initialization vector (or counter) in AES_IVRx.
Note: AES_IVRx concerns all modes except ECB.
- 4.Set the bit DATRDY (Data Ready) in the AES Interrupt Enable register (AES_IER), depending on whether an interrupt is required or not at the end of processing.
- 5.Write the data to be encrypted/decrypted in the authorized
AES_IDATARx (see the table below).
- 6.Set the START bit in the AES Control register (AES_CR) to begin the encryption or the decryption process.
- 7.When processing completes, the DATRDY flag in the AES Interrupt Status register (AES_ISR) is raised. If an interrupt has been enabled by setting AES_IER.DATRDY, the interrupt line of the AES is activated.
- 8.When software reads one of AES_ODATARx, AES_IER.DATRDY is
automatically cleared.
Table 1. Authorized Input Data Registers
Operating Mode |
Input Data Registers to Write |
ECB |
All |
CBC |
All |
OFB |
All |
128-bit CFB |
All |
64-bit CFB |
AES_IDATAR0 and
AES_IDATAR1 |
32-bit CFB |
AES_IDATAR0 |
16-bit CFB |
AES_IDATAR0 |
8-bit CFB |
AES_IDATAR0 |
CTR |
All |
GCM |
All |
Notes:
- 1.In 64-bit CFB mode, writing to AES_IDATAR2 and AES_IDATAR3 is not allowed and may
lead to errors in processing.
- 2.In 32, 16, and 8-bit CFB modes, writing to AES_IDATAR1, AES_IDATAR2 and AES_IDATAR3
is not allowed and may lead to errors in processing.