HSMCI Interrupt Enable Register
The following configuration values are valid for all listed bit names of this register:
0: No effect.
1: Enables the corresponding interrupt.
Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
UNRE | OVRE | ACKRCVE | ACKRCV | XFRDONE | FIFOEMPTY | BLKOVRE | |||
Access | |||||||||
Reset |
Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
CSTOE | DTOE | DCRCE | RTOE | RENDE | RCRCE | RDIRE | RINDE | ||
Access | |||||||||
Reset |
Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
CSRCV | SDIOWAIT | SDIOIRQA | |||||||
Access | |||||||||
Reset |
Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
NOTBUSY | DTIP | BLKE | TXRDY | RXRDY | CMDRDY | ||||
Access | |||||||||
Reset |
Command Ready Interrupt Enable
Receiver Ready Interrupt Enable
Transmit Ready Interrupt Enable
Data Block Ended Interrupt Enable
Data Transfer in Progress Interrupt Enable
Data Not Busy Interrupt Enable
SDIO Interrupt for Slot A Interrupt Enable
SDIO Read Wait Operation Status Interrupt Enable
Completion Signal Received Interrupt Enable
Response Index Error Interrupt Enable
Response Direction Error Interrupt Enable
Response CRC Error Interrupt Enable
Response End Bit Error Interrupt Enable
Response Time-out Error Interrupt Enable
Data CRC Error Interrupt Enable
Data Time-out Error Interrupt Enable
Completion Signal Timeout Error Interrupt Enable
DMA Block Overrun Error Interrupt Enable
FIFO empty Interrupt enable
Transfer Done Interrupt enable
Boot Acknowledge Interrupt Enable
Boot Acknowledge Error Interrupt Enable
Overrun Interrupt Enable
Underrun Interrupt Enable