SSC_IER

SSC Interrupt Enable Register

  0x44 32 Write-only –  

SSC Interrupt Enable Register

Bit  31 30 29 28 27 26 25 24  
                   
Access                   
Reset                   
Bit  23 22 21 20 19 18 17 16  
                   
Access                   
Reset                   
Bit  15 14 13 12 11 10 9 8  
          RXSYN TXSYN CP1 CP0  
Access          W W W W  
Reset           
Bit  7 6 5 4 3 2 1 0  
      OVRUN RXRDY     TXEMPTY TXRDY  
Access      W W     W W  
Reset           

Bit 0 – TXRDY: Transmit Ready Interrupt Enable

Transmit Ready Interrupt Enable

ValueDescription
0

No effect.

1

Enables the Transmit Ready Interrupt.

Bit 1 – TXEMPTY: Transmit Empty Interrupt Enable

Transmit Empty Interrupt Enable

ValueDescription
0

No effect.

1

Enables the Transmit Empty Interrupt.

Bit 4 – RXRDY: Receive Ready Interrupt Enable

Receive Ready Interrupt Enable

ValueDescription
0

No effect.

1

Enables the Receive Ready Interrupt.

Bit 5 – OVRUN: Receive Overrun Interrupt Enable

Receive Overrun Interrupt Enable

ValueDescription
0

No effect.

1

Enables the Receive Overrun Interrupt.

Bit 8 – CP0: Compare 0 Interrupt Enable

Compare 0 Interrupt Enable

ValueDescription
0

No effect.

1

Enables the Compare 0 Interrupt.

Bit 9 – CP1: Compare 1 Interrupt Enable

Compare 1 Interrupt Enable

ValueDescription
0

No effect.

1

Enables the Compare 1 Interrupt.

Bit 10 – TXSYN: Tx Sync Interrupt Enable

Tx Sync Interrupt Enable

ValueDescription
0

No effect.

1

Enables the Tx Sync Interrupt.

Bit 11 – RXSYN: Rx Sync Interrupt Enable

Rx Sync Interrupt Enable

ValueDescription
0

No effect.

1

Enables the Rx Sync Interrupt.