MCAN_NDAT2

MCAN New Data 2

  0x9C 32 Read/Write 0x00000000  
Parent topic: Register Summary

MCAN New Data 2

Bit  31 30 29 28 27 26 25 24  
  ND63 ND62 ND61 ND60 ND59 ND58 ND57 ND56  
Access  R/W R/W R/W R/W R/W R/W R/W R/W  
Reset  0 0 0 0 0 0 0 0  
Bit  23 22 21 20 19 18 17 16  
  ND55 ND54 ND53 ND52 ND51 ND50 ND49 ND48  
Access  R/W R/W R/W R/W R/W R/W R/W R/W  
Reset  0 0 0 0 0 0 0 0  
Bit  15 14 13 12 11 10 9 8  
  ND47 ND46 ND45 ND44 ND43 ND42 ND41 ND40  
Access  R/W R/W R/W R/W R/W R/W R/W R/W  
Reset  0 0 0 0 0 0 0 0  
Bit  7 6 5 4 3 2 1 0  
  ND39 ND38 ND37 ND36 ND35 ND34 ND33 ND32  
Access  R/W R/W R/W R/W R/W R/W R/W R/W  
Reset  0 0 0 0 0 0 0 0  

Bits 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31 – NDx: New Data

New Data

The register holds the New Data flags of Receive Buffers 32 to 63. The flags are set when the respective Receive Buffer has been updated from a received frame. The flags remain set until the processor clears them. A flag is cleared by writing a ‘1’ to the corresponding bit position. Writing a ‘0’ has no effect. A hard reset will clear the register.

ValueDescription
0

Receive Buffer not updated.
1

Receive Buffer updated from new message.