Bus Matrix Priority Registers A For Slaves
This register can only be written if the WPE bit is cleared in the Write Protection Mode Register.
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| M7PR[1:0] | M6PR[1:0] | ||||||||
| Access | R/W | R/W | R/W | R/W | |||||
| Reset | 0 | 0 | 0 | 0 | |||||
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| M5PR[1:0] | M4PR[1:0] | ||||||||
| Access | R/W | R/W | R/W | R/W | |||||
| Reset | 0 | 0 | 0 | 0 | |||||
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| M3PR[1:0] | M2PR[1:0] | ||||||||
| Access | R/W | R/W | R/W | R/W | |||||
| Reset | 0 | 0 | 1 | 0 | |||||
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| M1PR[1:0] | M0PR[1:0] | ||||||||
| Access | R/W | R/W | R/W | R/W | |||||
| Reset | 1 | 0 | 1 | 0 | |||||
Master x Priority
Fixed priority of Master x for accessing the selected slave. The higher the number, the higher the priority.
All the masters programmed with the same MxPR value for the slave make up a priority pool.
Round-robin arbitration is used in the lowest (MxPR = 0) and highest (MxPR = 3) priority pools.
Fixed priority is used in intermediate priority pools (MxPR = 1) and (MxPR = 2).
See “Arbitration Priority Scheme” for details.