GMAC PHY Maintenance Register
This register is a shift register. Writing to it starts a shift operation which is signaled completed when bit 2 is set in the Network Status Register (GMAC_NSR). It takes about 2000 MCK cycles to complete, when MDC is set for MCK divide by 32 in the Network Configuration Register. An interrupt is generated upon completion.
During this time, the MSB of the register is output on the MDIO pin and the LSB updated from the MDIO pin with each MDC cycle. This causes transmission of a PHY management frame on MDIO. Refer also to section 22.2.4.5 of the IEEE 802.3 standard.
Reading during the shift operation returns the current contents of the shift register. At the end of management operation, the bits will have shifted back to their original locations. For a read operation, the data bits are updated with data read from the PHY. It is important to write the correct values to the register to ensure a valid PHY management frame is produced.
The MDIO interface can read IEEE 802.3 clause 45 PHYs, as well as clause 22 PHYs. To read clause 45 PHYs, bit 30 should be written with a '0' rather than a '1'. To write clause 45 PHYs, bits 31:28 should be written as 0x1:
| PHY | Access | Bit Value | |||
|---|---|---|---|---|---|
| WZO | CLTTO | OP[1] | OP[0] | ||
| Clause 22 | Read | 0 | 1 | 1 | 0 |
| Write | 0 | 1 | 0 | 1 | |
| Clause 45 | Read | 0 | 0 | 1 | 1 |
| Write | 0 | 0 | 0 | 1 | |
| Read + Address | 0 | 0 | 1 | 0 | |
For a description of MDC generation, see also the 'GMAC Network Configuration Register' (GMAC_NCR) description.
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| WZO | CLTTO | OP[1:0] | PHYA[4:1] | ||||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| PHYA[0] | REGA[4:0] | WTN[1:0] | |||||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| DATA[15:8] | |||||||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| DATA[7:0] | |||||||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
PHY Data
For a write operation, this field is written with the data to be written to the PHY.
After a read operation, this field contains the data read from the PHY.
Write Ten
Must be written to '10'.
| Value | Description |
|---|---|
| 10 | Mandatory |
| Other | Reserved |
Register Address
Specifies the register in the PHY to access.
PHY Address
Operation
| Value | Description |
|---|---|
| 01 | Write |
| 10 | Read |
| Other | Reseved |
Clause 22 Operation
| Value | Description |
|---|---|
| 0 | Clause 45 operation |
| 1 | Clause 22 operation |
Write ZERO
Must be written to '0'.
| Value | Description |
|---|---|
| 0 | Mandatory |
| 1 | Reserved |