A general reset occurs when a VDDIO POR is detected, a brown out or a voltage regulation loss is detected by the Supply Controller. The vddcore_nreset signal is asserted by the Supply Controller when a general reset occurs.
All the reset signals are released and RSTC_SR.RSTTYP reports a general reset. As the RSTC_MR is written to ‘0’, the NRST line rises two cycles after the vddcore_nreset, as ERSTL defaults at value 0x0.
The figure below ilustrates how the general reset affects the reset signals.
Figure 1. General Reset Timing Diagram
