PMC_PCER0

PMC Peripheral Clock Enable Register 0

This register can only be written if the WPEN bit is cleared in the PMC Write Protection Mode Register.

  0x0010 32 Write-only    
Parent topic: Register Summary

PMC Peripheral Clock Enable Register 0

Bit  31 30 29 28 27 26 25 24  
  PID31 PID30 PID29 PID28 PID27 PID26 PID25 PID24  
Access                   
Reset                   
Bit  23 22 21 20 19 18 17 16  
  PID23 PID22 PID21 PID20 PID19 PID18 PID17 PID16  
Access                   
Reset                   
Bit  15 14 13 12 11 10 9 8  
  PID15 PID14 PID13 PID12 PID11 PID10 PID9 PID8  
Access                   
Reset                   
Bit  7 6 5 4 3 2 1 0  
  PID7                
Access                   
Reset                   

Bits 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31 – PIDx: Peripheral Clock x Enable

Peripheral Clock x Enable

ValueDescription
0

No effect.
1

Enables the corresponding peripheral clock.

Notes:
  1. 1.PIDx refers to identifiers defined in the section “Peripheral Identifiers”. Other peripherals can be enabled in PMC_PCER1 (see PMC_PCER1).
  2. 2.Programming the control bits of the Peripheral ID that are not implemented has no effect on the behavior of the PMC.