PMC Clock Generator PLLA Register
Possible limitations on PLLA input frequencies and multiplier factors should be checked before using the PMC.
This register can only be written if the WPEN bit is cleared in the PMC Write Protection Mode Register.
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| ONE | MULA[10:8] | ||||||||
| Access | |||||||||
| Reset | 0 | 0 | 0 | 0 | |||||
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| MULA[7:0] | |||||||||
| Access | |||||||||
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| PLLACOUNT[5:0] | |||||||||
| Access | |||||||||
| Reset | 1 | 1 | 1 | 1 | 1 | 1 | |||
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| DIVA[7:0] | |||||||||
| Access | |||||||||
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
PLLA Front End Divider
| Value | Name | Description |
|---|---|---|
| 0 | 0 | PLLA is disabled. |
| 1 | BYPASS | Divider is bypassed (divide by 1) and PLLA is enabled. |
| 2–255 | Divider output is the selected clock divided by DIVA. |
PLLA Counter
Specifies the number of SLCK cycles before the LOCKA bit is set in PMC_SR after CKGR_PLLAR is written.
PLLA Multiplier
1 up to 62 = PLLCK frequency is the PLLA input frequency multiplied by MULA + 1.
Unlisted values are forbidden.
| Value | Description |
|---|---|
| 0 | The PLLA is disabled (PLLA also disabled if DIVA = 0). |
Must Be Set to 1
Bit 29 must always be set to ‘1’ when programming the CKGR_PLLAR.