SMC_KEY2

SMC Off-Chip Memory Scrambling Key2 Register

Note: ‘Write-once’ access indicates that the first write access after a system reset prevents any further modification of the value of this register.
  0x88 32 Write-once 0x00000000  
Parent topic: Static Memory Controller (SMC) User Interface

SMC Off-Chip Memory Scrambling Key2 Register

Bit  31 30 29 28 27 26 25 24  
  KEY2[31:24]  
Access                   
Reset  0 0 0 0 0 0 0 0  
Bit  23 22 21 20 19 18 17 16  
  KEY2[23:16]  
Access                   
Reset  0 0 0 0 0 0 0 0  
Bit  15 14 13 12 11 10 9 8  
  KEY2[15:8]  
Access                   
Reset  0 0 0 0 0 0 0 0  
Bit  7 6 5 4 3 2 1 0  
  KEY2[7:0]  
Access                   
Reset  0 0 0 0 0 0 0 0  

Bits 31:0 – KEY2[31:0]: Off-Chip Memory Scrambling (OCMS) Key Part 2

Off-Chip Memory Scrambling (OCMS) Key Part 2

When off-chip memory scrambling is enabled, KEY1 and KEY2 values determine data scrambling.